IBM proved its 0.7nm chip works. The factory to make it doesn’t exist yet

IBM’s research laboratory in Albany, New York has built a functional chip at 0.7 nanometers — below the 1nm threshold that many engineers believed would take the industry a decade to reach. The chip carries nearly 100 billion transistors in a fingernail-sized area. The lab demonstration is genuine. Commercial production is at least five years away.

The architecture is called nanostack, and it works by arranging transistors in two vertical tiers instead of a single flat layer. Each tier holds three nanosheets, each 15 atoms thick, and the tiers are staggered — offset rather than aligned. That staggering simplifies how electrical connections between layers are routed and reduces the failure rate that would otherwise make the design impractical at scale. TSMC’s 2nm process, the current commercial benchmark shipping in volume this year, uses a flat single-tier nanosheet design. IBM has added a second floor.

The performance difference over IBM’s own 2nm chip from 2021 is significant: 50% more compute at the same power draw, or 70% greater energy efficiency for the same workload. SRAM density improves by 40%. For AI data center operators, who collectively spent roughly $300 billion on compute infrastructure in 2025, that 70% efficiency figure is not an abstract benchmark. Running large AI models at 70% of current energy cost would change the economics of data center construction, reduce the electricity bills that are now the dominant operating cost of AI inference, and shrink the infrastructure footprint that countries are being asked to build.

IBM collaborated with Lam Research, Tokyo Electron, SCREEN, and ASML on the process tools required for nanostack manufacturing. None of those companies has announced a production timeline. IBM’s own roadmap projects commercial adoption in as early as five years; MIT Technology Review’s analysis, drawing on the same data, puts widespread deployment at ten. The reasons for the gap are engineering. Stacking transistors vertically multiplies failure modes — a defect in the top tier can corrupt the electrical connection to the layer below in ways that flat architectures do not face. The thermal budget is narrow: everything in the second-tier build process must stay below 400°C, because higher temperatures degrade the connections already built into the first tier. At research scale this is manageable. At ten billion transistors per chip and billions of chips per year, it is the constraint that determines whether a laboratory result becomes a commercial product.

What nanostack establishes is that transistor density can still double. The question that has circled the semiconductor industry for years — whether Moore’s Law had reached a physical wall — has an answer: not yet. The path forward is vertical. IBM’s semiconductor roadmap projects at least a decade of further scaling using nanostack-based architectures. The first commercial chips at this density are expected no earlier than 2031.

Tags: semiconductors, TSMC, ASML, IBM, Moore's Law, nanostack