AMD’s EPYC Venice is the first server chip on 2nm — 256 cores and 1.6 TB/s of memory bandwidth

The semiconductor industry crossed a threshold on July 22. AMD announced at its Advancing AI 2026 event that EPYC Venice — the sixth generation of its server CPU line, built on the Zen 6 architecture — is entering volume production on TSMC’s 2nm process node. No high-performance computing chip has shipped at 2nm before. Venice is the first.

The headline configuration seats 256 cores and 512 threads across eight Core Complex Dies, each housing 32 Zen 6 cores — a 33% increase in core density over the previous CCD design. The platform introduces a new SP7 socket with 16 memory channels, bringing aggregate bandwidth to 1.6 TB/s, nearly three times the 614 GB/s of the outgoing Turin generation. PCIe Gen 6 at 64 Gbps and a fifth-generation Infinity Fabric round out the interconnect stack.

TSMC’s 2nm node makes the jump from FinFET to GAA (gate-all-around) nanosheet transistors — a structural change that TSMC rates at 10 to 15% higher performance at the same power envelope, or 25 to 30% lower power at equivalent performance, with 15% greater transistor density. AMD’s own benchmark claim is a 70% CPU throughput improvement over Turin’s Zen 5 cores. In AI inference workloads, AMD is claiming 2.2 times the throughput of NVIDIA‘s competing Vera platform at the 256-core tier.

Venice ships in four product lines. The flagship EPYC 9006 SP7 is the 256-core Agentic AI part with 5 GHz boost and 128 PCIe Gen6 lanes. The EPYC 9006X SP7 tops out at 96 cores but runs 5.15 GHz with three times the L3 cache per core — targeting HPC and simulation workloads where latency matters more than raw parallelism. An SP8 line covers edge and power-constrained deployments with 8 to 128 cores. A fourth SKU, the EPYC 9006 LP Verano, carries LPDDR5X memory and 112 Gbps CPU-to-GPU bandwidth for rack-scale AI chassis.

The total L3 cache across the flagship SKU reaches 1,152 MB of 3D V-Cache — a number that becomes relevant for AI model layers that can be kept on-die rather than returning to DRAM. AMD has not disclosed pricing for any Venice variant. Cloud providers and OEMs are expected to announce availability windows independently, with several major hyperscalers already confirmed as early customers.

The competitive context matters. Intel’s next Granite Rapids-D generation is still on Intel 18A, which remains months from volume yield at the scale required for a product like this. NVIDIA’s shift toward its own CPU silicon with Vera and Grace means the GPU vendor is now also a direct competitor in the CPU socket. Venice lands before either alternative reaches comparable production scale, which historically translates into win rates at cloud procurement cycles that run 12 to 18 months out.

For AI workload operators, the memory bandwidth figure is the most immediately relevant. Training and inference at scale are primarily bandwidth-constrained operations, and doubling effective bandwidth per rack node changes the cost-per-token math in a measurable way. Cloud operators who have been holding large GPU reservations partly to compensate for CPU bottlenecks now have an alternative path. That arithmetic will sort itself out across the next two procurement seasons.

Tags: AMD, EPYC Venice, HPC, server CPU, TSMC 2nm, Zen 6